XR16C850CM-F Datasheet, PDF (12/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
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REV. 2.3.1
2.7 Internal Registers
The 850 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad register
(SPR).
Beyond the general 16C550 features and capabilities, the 850 offers enhanced feature registers (EMSR, TRG,
FC, FCTR, EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, Xon/Xoff
software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level control,
and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0, UART
INTERNAL REGISTERS” on page 25.
2.8 DMA Mode
The DMA Mode (a legacy term) in this document does not mean “Direct Memory Access” but refers to data
block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins.
The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation.
The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data.
The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the
transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 850 activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1),
the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence
determined by the programmed trigger level. In this mode, the 850 sets the TXRDY# pin when the transmit
FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table
shows their behavior.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
RXRDY# A/B
TXRDY# A/B
FCR BIT-0=0
(FIFO DISABLED)
0 = 1 byte.
1 = no data.
0 = THR empty.
1 = byte in THR.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
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