XR16C850CM-F Datasheet, PDF (50/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
xr
REV. 2.3.1
FIGURE 27. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
Start
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
Stop
Bit
INT
T_SSR
RXRDY#
First Byte is
Received in
RX FIFO
T_SSI
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
T_RRI
T_RR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
RX
INT
RXRDY#
Start
Bit
Stop
Bit
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
T_SSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
T_SSR
Timeout
FIFO
Empties
IOR#
(Reading data out
of RX FIFO)
T_RRI
T_RR
RXFIFODMA
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