XR16C850CM-F Datasheet, PDF (55/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

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REV. 2.3.1
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
FEATURES ..................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PINOUTS IN INTEL BUS MODE AND PC MODE, TQFP AND PLCC PACKAGES ................................................................... 2
PIN DESCRIPTIONS .......................................................................................................... 3
Intel Bus Mode Interface. The SEL pin is connected to VCC. ..................................................................................... 3
ORDERING INFORMATION ................................................................................................................................ 3
PC Mode Interface Signals. Connect SEL pin to GND to select PC Mode. ................................................................ 5
MODEM OR SERIAL I/O INTERFACE ....................................................................................................................... 6
ANCILLARY SIGNALS ................................................................................................................................................ 6
1.0 PRODUCT DESCRIPTION .................................................................................................................... 8
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 9
2.1 HOST DATA BUS INTERFACE ....................................................................................................................... 9
FIGURE 3. XR16C850 INTEL BUS INTERCONNECTIONS .................................................................................................................... 9
FIGURE 4. XR16C850 PC MODE INTERCONNECTIONS...................................................................................................................... 9
2.2 PC MODE ........................................................................................................................................................ 10
TABLE 1: PC MODE INTERFACE ON-CHIP ADDRESS DECODER AND INTERRUPT SELECTION.............................................................. 10
FIGURE 5. PC MODE INTERFACE IN AN EMBEDDED APPLICATION..................................................................................................... 10
2.3 16-BIT BUS INTERFACE ............................................................................................................................... 11
FIGURE 6. XR16C850 16-BIT BUS INTERFACE.............................................................................................................................. 11
2.4 5-VOLT TOLERANT INPUTS ......................................................................................................................... 11
2.5 DEVICE RESET .............................................................................................................................................. 11
2.6 DEVICE IDENTIFICATION AND REVISION .................................................................................................. 11
2.7 INTERNAL REGISTERS ................................................................................................................................. 12
2.8 DMA MODE .................................................................................................................................................... 12
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE........................................................................................... 12
2.9 INTERRUPTS ................................................................................................................................................. 13
TABLE 3: INTERRUPT OUTPUT FUNCTIONS ...................................................................................................................................... 13
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 13
2.10 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ..................................................................................... 13
2.11 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 14
FIGURE 8. BAUD RATE GENERATOR ............................................................................................................................................... 14
TABLE 4: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 14
2.12 TRANSMITTER ............................................................................................................................................. 15
2.12.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 15
2.12.2 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 15
FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 15
2.12.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 15
FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 16
2.13 RECEIVER .................................................................................................................................................... 16
2.13.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 16
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 17
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 17
2.14 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 18
2.15 AUTO RTS HYSTERESIS ........................................................................................................................... 18
TABLE 5: AUTO RTS HYSTERESIS.................................................................................................................................................. 18
2.16 AUTO CTS (HARDWARE) FLOW CONTROL ............................................................................................ 19
FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19
2.17 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 20
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 20
2.18 SPECIAL CHARACTER DETECT ............................................................................................................... 20
2.19 AUTO RS485 HALF-DUPLEX CONTROL .................................................................................................. 20
FIGURE 14. AUTO RS-485 HALF-DUPLEX CONTROL ....................................................................................................................... 21
2.20 INFRARED MODE ........................................................................................................................................ 21
FIGURE 15. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 22
2.21 SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 23
2.22 INTERNAL LOOPBACK .............................................................................................................................. 24
FIGURE 16. INTERNAL LOOPBACK................................................................................................................................................... 24
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