XRT75L00D Datasheet, PDF (6/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 28
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 28
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 29
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................. 29
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.............................................................................................................. 29
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: .......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 30
DISABLING ALOS/DLOS DETECTOR:............................................................................................................30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1
APPLICATIONS) ............................................................................................................................................................... 30
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION: ................................................................................... 31
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 31
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 31
6.0 JITTER: ................................................................................................................................................32
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 32
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS: ............................................................................................... 32
FIGURE 21. JITTER TOLERANCE MEASUREMENTS............................................................................................................................ 32
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 33
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ................................................................................................................ 33
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 33
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 34
6.3 JITTER GENERATION: .................................................................................................................................. 34
6.4 JITTER ATTENUATOR: ................................................................................................................................. 34
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)................................................................... 34
TABLE 12: JITTER TRANSFER SPECIFICATIONS................................................................................................................................ 34
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 35
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 35
7.0 SERIAL HOST INTERFACE: ...............................................................................................................36
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 36
TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 36
TABLE 16: REGISTER MAP DESCRIPTION ........................................................................................................................................ 37
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL......................................................................................................................... 41
8.0 DIAGNOSTIC FEATURES: ..................................................................................................................42
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 42
8.2 LOOPBACKS: ................................................................................................................................................. 43
FIGURE 25. PRBS MODE ............................................................................................................................................................. 43
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 44
8.2.2 DIGITAL LOOPBACK: ................................................................................................................................................ 44
FIGURE 26. ANALOG LOOPBACK ..................................................................................................................................................... 44
8.2.3 REMOTE LOOPBACK: ............................................................................................................................................... 45
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 45
FIGURE 27. DIGITAL LOOPBACK...................................................................................................................................................... 45
FIGURE 28. REMOTE LOOPBACK .................................................................................................................................................... 45
FIGURE 29. TRANSMIT ALL ONES (TAOS) ...................................................................................................................................... 46
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ...............................................................47
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ............................ 47
FIGURE 30. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ........ 48
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 49
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 49
9.2.1.1 A BRIEF DESCRIPTION OF AN STS-1 FRAME ......................................................................................................... 49
FIGURE 31. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME .............................................................................................. 50
FIGURE 32. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
51
FIGURE 33. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 52
FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 53
9.2.1.2 MAPPING DS3 DATA INTO AN STS-1 SPE ............................................................................................................ 54
FIGURE 35. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE....................................................................................... 54
FIGURE 36. AN ILLUSTRATION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE... 55
FIGURE 37. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO
AN STS-1 SPE .............................................................................................................................................................. 55
9.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 56
9.2.2.1 THE IDEAL CASE FOR MAPPING DS3 DATA INTO AN STS-1 SIGNAL (E.G., WITH NO FREQUENCY OFFSETS) ............ 57
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