XRT75L00D Datasheet, PDF (46/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x07 R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
0
ator as shown in the table below.
JA0
JA1
Mode
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
128 bit FIFO
1
1
Disable Jitter
Attenuator
0x08
D1
JATx/Rx Writing a “1” to this bit selects the Jitter Attenuator in
0
the Transmit Path. A “0” selects in the Receive Path.
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
0
uator as shown in the table.
D3
PNTRST Setting this bit to “1” resets the Read and Write point-
0
ers of the jitter attenuator FIFO.
D4
DFLCK Set this bit to "1" to disable the SONET APS Recov-
0
ery Time of the PLL. When this bit is "0", the APS
Recovery Time is enabled. This helps to reduce the
time for the PLL to lock to the incoming frequency
when the Jitter Attenuator switches to narrow band.
This is required for SONET to DS-3 Mapping/Demap-
ping De-Synchronization applications.
Reserved
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)
0x20
TYPE
R/W
0x21
Read
Only
0x22 -
0x2F
0x30
0x31
Reset
Upon
Read
Reset
Upon
Read
BIT
LOCATION
D0
D0
D[7:0]
D[7:0]
SYMBOL
INTEN
INTST
DESCRIPTION
DEFAULT
VALUE(BIN)
Bit 0 = INTEN Writing a “1” to this bit enables the
0
interrupts.
Bit 0 = INTST bit is set to “1” if an interrupt service is
0
required. The source level interrupt status register is
read to determine the cause of interrupt.
Reserved
PRBSmsb PRBS error counter MSB [15:8]
PRBSlsb PRBS error counter LSB [7:0]
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