XRT75L00D Datasheet, PDF (37/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.2
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
6.0 JITTER:
There are three fundamental parameters that describe circuit performance relative to jitter:
• Jitter Tolerance (Receiver)
• Jitter Transfer (Receiver/Transmitter)
• Jitter Generation
6.1 JITTER TOLERANCE - RECEIVER:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
FIGURE 21. JITTER TOLERANCE MEASUREMENTS
Pattern
Data
GenPeartatetornr
Generator
Modulation
Freq.
FREQ
SynthFeRsEizQer
Synthesizer
DUT
XRT7D5LU0T0D
XRT75L00D
Clock
Error
DetEecrrtoorr
Detector
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
6.1.1 DS3/STS-1 Jitter Tolerance Requirements:
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification along with the measured performance for the
device.
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