XRT75L00D Datasheet, PDF (34/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
NOISE
N
GENERATOR
ATTENUATOR 1 ATTENUATOR 2
Cable Simulator
DUT
XRT75L00D
Test Equipment
Pattern
S
Generator
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE
E3
DS3
STS-1
CABLE LENGTH (ATTENUATION)
0 dB
12 dB
0 feet
225 feet
450 feet
0 feet
225 feet
450 feet
INTERFERENCE TOLERANCE
-14 dB
-18 dB
-17 dB
-16 dB
-16 dB
-16 dB
-15 dB
-15 dB
5.2 Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and
provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
TRAINING MODE:
In the absence of input signals at RTIP and RRing pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk input pin exceed 0.5%, the clock
recovery unit enters into Training Mode and a Loss of Lock condition is declared by toggling RLOL output pin
“High” (in Hardware Mode) or setting the RLOL bit to “1” in the control registers (in Host Mode). Also, the clock
output on the RxClk pin is the same as the reference clock applied on ExClk pin.
DATA/CLOCK RECOVERY MODE:
In the presence of input line signals on the RTIP and RRing input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk out pin is the Recovered Clock signal.
5.3 B3ZS/HDB3 Decoder:
29