XRT75L00D Datasheet, PDF (44/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x03 Read
D0
Only
DMO
This bit is set to “1” every time the MTIP/MRing input
0
pins have not detected any bipolar pulses for 128
consecutive bit periods.
D1
RLOS This bit is set to “1” every time the receiver declares
0
an LOS condition.
D2
RLOL This bit is set to “1” every time when the receiver
0
declares a Loss of Lock condition.
D3
FL
This bit is set to “1” every time the FIFO in the Jitter
0
Attenuator is within 2 bit of underflow/overflow condi-
tion.
D4
ALOS This bit is set to “1” every time the receiver declares
0
Analog LOS condition.
D5
DLOS This bit is set to “1” every time the receiver declares
0
Digital LOS condition.
D6
PRBSLS This bit is set to “1” every time the PRBS detects a bit
0
error.
0x04 R/W
D0
TxLEV Writing a “1” to this bit disables the Transmit Build-out
0
circuit and writing a “0” enables the Transmit Build-out
circuit.
NOTE: See section 4.03 for detailed description.
D1
TxClkINV Writing a “1” to this bit configures the transmitter to
0
sample the data on TPData/TNData input pins on the
rising edge of TxClk.
D2
TAOS Setting this bit to “1” causes a continuous stream of
0
marks to be sent out at the TTIP and TRing pins.
D3
Reserved This Bit Location is Not Used.
D4
INSPRBS Writing a “1” to this bit causes the PRBS generator to
0
insert a single-bit error onto the transmit PRBS data
stream.
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
D5
TxMON When this bit is set to “1”, the driver monitor is con-
0
nected to its own transmit channel and monitors the
transmit driver. When a transmit failure is detected,
the DMO output will go high.
When this bit is “0”, MTIP and MRing can be con-
nected to other transmit channel for monitoring.
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