XRT75L00D Datasheet, PDF (2/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
• Fiber Optic Terminals.
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L00D
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
LLB
TTIP
TRING
MTIP
MRING
DMO
Serial
Processor
Interface
XRT75L03
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
MUX
Attenuator
Remote
LoopBack
Invert
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
REV. 1.0.2
CLK_OUT
ExClk/12M
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
RLB
RLOS
JATx/Rx
TPData
TNData
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
• Integrated Pulse Shaping Circuit.
• Built-in B3ZS/HDB3 Encoder (which can be disabled).
• Accepts Transmit Clock with duty cycle of 30%-70%.
• Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
• Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993.
• Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.
• Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
• Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
• Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
• Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.
• Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
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