XRT75L00D Datasheet, PDF (49/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.2
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
8.2.1 ANALOG LOOPBACK:
In this mode, the transmitter outputs (TTIP and TRING) are connected internally to the receiver inputs (RTIP
and RRING) as shown in Figure 26. Data and clock are output at RCLK, RPOS and RNEG pins for the
corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the
jitter attenuator which can be selected in either the transmit or receive path.
XRT75L00D can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in
Host mode via LLB and RLB bits in the channel control registers.
NOTES:
1. In the Analog loopback mode, data is also output via TTIP and TRING pins.
2. Signals on the RTIP and RRING pins are ignored during analog loopback.
FIGURE 26. ANALOG LOOPBACK
TCLK
TPDATA
TNDATA
HDB3/B3ZS¹
ENCODER
TIMING
CONTROL
Tx
TTIP
TRING
RCLK
RPOS
RNEG
HDB3/B3ZS¹
DECODER
DATA &
CLOCK
Rx
RECOVERY
1 _{if enabled}
2 _{if enabled and selected in either Receive or Transmit path}
RTIP
RRING
8.2.2 DIGITAL LOOPBACK:
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and
output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA
and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
NOTE: Signals on the RTIP and RRING pins are ignored during digital loopback.
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