NS9360B-0-C177 Datasheet, PDF (49/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

SDRAM timing
SDRAM write
SDRAM write
T1
T2
T1
prechg
active
write
inhibit
BCLK
TA* (Note-3)
30
30
TEA*/LAST* (Note-3)
31
31
PortA2/AMUX
37
37
6
Non-muxed address
35
35
Muxed address
36
36
BE[3:0]* (DQM) ^Note-1
9
13
write D[31:0]
27
27
CS[4:0]*
34
34
CAS3* (RAS)
CAS2* (CAS)
34
34
34
34
34
34
CAS1* (WE)
CAS0* (A10/AP)
34
34
34
A10
12
RW*
Notes:
1 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:2]
– 32-bit port = BE[3:0]
2 The precharge and/or active commands are not always present. These commands depend on
the address of the previous SDRAM access.
3 The TA* and TEA*/LAST signals are for reference only.
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