NS9360B-0-C177 Datasheet, PDF (38/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

SRAM timing
SRAM write
CS controlled write (internal and external), (wait = 2)
BCLK
TA* (Note-4)
TEA* (Note-4)
T1
TW
TA* (input)
6
A[27:0]
36
BE[3:0]* ^Note-2
27
CS[4:0]*
9
write D[31:0]
29
Sync WE*
19
CS0WE*
12
RW*
TW
T2
Note-1
T1
30
31
14
30
31
15
36
27
13
29
19
Notes:
1 If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock
pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:0]
– 32-bit port = BE[3:0]
3 The TW cycles are present when the WAIT field is set to 2 or more.
4 The TA* and TEA*/LAST signals are for reference only.
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NS7520 Datasheet 03/2006