NS9360B-0-C177 Datasheet, PDF (26/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

NS7520 bootstrap initialization
NS7520 bootstrap initialization
Many internal NS7520 features are configured when the RESET pin is asserted. The address bus
configures the appropriate control register bits at powerup. This table shows which bits control
which functions:
Address bit
ADDR[27]
ADDR[26]
ADDR[24:23]
Name
Endian configuration
CPU bootstrap
CS0/MMCR[19:18] setting
ADDR[19:9]
ADDR[8:7]
ADDR[6:5]
ADDR[4:0]
GEN_ID setting
PLL IS setting
PLL FS setting
PLL ND setting
Table 3: NS7520 test modes
Description
0 Little Endian configuration
1 Big Endian configuration
0 CPU disabled; GEN_BUSER=1
1 CPU enabled; GEN_BUSER=0
00 8-bit SRAM, 63 wait-states/b00
01 32-bit SRAM, 63 wait-states/b01
10 32-bit SRAM
11 16-bit SRAM, 63 wait-states/b11
GEN_ID=A[19:09],default=’h3ff
IS=A[8:7], default=’b10
FS=A[6:5], default=’b00
ND=A[4:0], default=’b01011
JTAG
The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520 pins can be
controlled using the JTAG interface port. The JTAG interface provides access to the ARM7TDMI
debug module when the appropriate combination of PLLTST_, BISTEN_, and SCANEN_ is selected (as
shown in Table 3: "NS7520 test modes").
ARM Debug
The ARM7TDMI core uses a JTAG TAP controller that shares the pins with the TAP controller used for
1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller,
{PLLTST_,BISTEN_,SCANEN_} must be set as shown in Table 3: "NS7520 test modes".
22
NS7520 Datasheet 03/2006