NS9360B-0-C177 Datasheet, PDF (30/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

AC electrical specifications
SDRAM
SDRAM
NS7520
Buffer
other
memory
devices
Figure 7: System configuration for specified timing
Signal
BCLK
Estimated load (pF)
23
A[27:0], CAS[3:0]_
23
CS[4:0]_
13
DATA[31:0]
18
BE*_
19
TS_, TA_, TEA_, BR_, BG_, BUSY_, WE_, 15
OE_
PORTA3, PORTA1, PORTC3, PORTC1 15
(operating external DMA)
Other PORTA[*] and PORTC[*], TDO
85
MDC, MDIO, TXEN, TXER, TXD[3:0]
20
Device loads
Two SDRAMs, 1 clock buffer/clock
input to PLD
Two SDRAM An, 1 buffer/PLD
Two SDRAM CSn, 1 buffer PLD
One SDRAM DQ, 1 buffer/PLD
One SDRAM DQ, 1 buffer/PLD
1 buffer/PLD
1 buffer/PLD
Tester load
One PHY
Table 7: System loading details
Exceeding the loading shown in Table 7 can result in additional signal delay. The delay can be
approximated by derating the output buffer based on the expected load capacitance per the values
shown in Table 8.
Signal
Derating (ns/pF)
BCLK
0.069
A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0] 0.150
BE[3:0]
0.300
Table 8: Output buffer derating by load capacitance
26
NS7520 Datasheet 03/2006