NS9360B-0-C177 Datasheet, PDF (18/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

General Purpose I/O
GPIO signal Serial
signal
PORTC5
PORTC4¹
RTSB_
RXCB/RIB_/
OUT1B_
Other
signal
REJECT_
RESET_
Pin I/O OD
F15 U I/O 2
F12 U I/O 2
PORTC3²
RXDB
PORTC2²
PORTC1²
DSRB_
CTSB_
PORTC0²
TXCB/
OUT2B_/
DCDB_
LIRQ3/
DACK2_
F13 U I/O 2
LIRQ2/RPSF_ E15 U I/O 2
LIRQ1/
E12 U I/O 2
DONE2_(O)
LIRQ0/
DONE2_(I)
E14 U I/O 2
Serial channel Other
description
description
Channel 2 RTS_ CAM reject
Pgm’able Out/
Channel 2
RXCLK/Channel 2
ring signal/
Channel 2 SPI
clock (CLK)
RESET output
Channel 2 RXD
Level sensitive IRQ /
DMA channel 4/6
ACK
Channel 2 DSR_ Level sensitive IRQ/
CAM request
Channel 2 CTS_
Level sensitive IRQ /
DMA channel 4/6
DONE_Out
Pgm’able Out/
Channel 2 DCD/
Channel 2 SPI
enable (SEL_)/
Channel 2 TXCLK
Level sensitive IRQ /
DMA channel 4/6
DONE_In
Notes:
1 RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of
RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled,
PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds
times the ratio of the VCO to XTALA.
This GPIO is left in output mode active following a hardware RESET.
2 PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous
to any clock. The interrupt remains active until cleared by a change in the input signal level.
14
NS7520 Datasheet 03/2006