NS9360B-0-C177 Datasheet, PDF (37/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

SRAM timing
SRAM burst read (2111)
CS* controlled read (wait = 0, BCYC = 00)
T1
T2
T2
BCLK
30
TA* (Note-3)
TEA* (Note-3)
6
A[27:0]
36
BE[3:0]* ^Note-2
27
CS[4:0]*
read D[31:0]
11
10
28
Sync OE*
18
CS0OE*
12
RW*
T2
T2
Note-1
T1
30
31
31
36
27
28
18
Notes:
1 If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock
pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:0]
– 32-bit port = BE[3:0]
3 The TA* and TEA*/LAST signals are for reference only.
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