NS9360B-0-C177 Datasheet, PDF (14/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

Chip select controller
Chip select controller
The NS7520 supports five unique chip select configurations.
Symbol
CS4_
CS3_
CS2_
CS1_
CS0_
CAS3_
CAS2_
CAS1_
CAS0_
WE_
OE_
Pin
I/O OD Description
B4
O
4
Chip select/DRAM RAS_
A4
O
4
Chip select/DRAM RAS_
C5
O
4
Chip select/DRAM RAS_
B5
O
4
Chip select/DRAM RAS_
D5
O
4
Chip select (boot select)
A1
O
4
FP/EDO DRAM column strobe D31:D24/SDRAM RAS_
C4
O
4
FP/EDO DRAM column strobe D23:D16/SDRAM CAS_
B3
O
4
FP/EDO DRAM column strobe D15:D08/SDRAM WE_
A2
O
4
FP/EDO DRAM column strobe D07:D00/SDRAM A10(AP)
C6
O
4
Write enable for NCC Ctrl’d cycles
B6
O
4
Output enable for NCC Ctrl’d cycles
Chip select controller signal descriptions
Mnemonic
CS0_
CS1_
CS2_
CS3_
CS4_
Signal
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
CAS0_
CAS1_
CAS2_
CAS3_
Column address
strobe signals
WE_
OE_
Write enable
Output enable
Description
Unique chip select outputs supported by the NS7520. Each chip select
can be configured to decode a portion of the available address space
and can address a maximum of 256 Mbytes of address space. The
chip selects are configured using registers in the memory module.
A chip select signal is driven low to indicate the end of the current
memory cycle. For FP/EDO DRAM, these signals provide the RAS
signal.
Activated when an address is decoded by a chip select module
configured for DRAM mode. The CAS_ signals are active low and
provide the column address strobe function for DRAM devices.
The CAS_ signals also identify which 8-bit bytes of the 32-bit data bus
are active during any given system bus memory cycle.
For SDRAM, CAS[3:1]_ provides the SDRAM command field. CAS0_
provides the auto-precharge signal.
For non-DRAM settings, these signals are 1.
Active low signal that indicates that a memory write cycle is in
progress. This signal is activated only during write cycles to
peripherals controlled by one of the chip selects in the memory
module.
Active low signal that indicates that a memory read cycle is in
progress. This signal is activated only during read cycles from
peripherals controlled by one of the chip selects in the memory
module.
10
NS7520 Datasheet 03/2006