NS9360B-0-C177 Datasheet, PDF (42/68 Pages) List of Unclassifed Manufacturers – This table lists the key features of the NS7520

SRAM timing
SRAM WE write
WE* controlled write (wait = 2)
T1
TW
T2
Note-1
T1
BCLK
TA* (Note-4)
TEA*/LAST (note-4)
TA* (input)
A[27:0]
BE[3:0]*
6
36
Note-2
CS[4:0]*
write D[31:0]
Async WE*
CS0WE*
12
RW*
30
30
31
31
15
14
27
9
29
19
36
27
13
29
19
Notes:
1 At least one null period occurs between memory transfers. More null periods can occur if the
next transfer is DMA. Thirteen clock pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:0]
– 32-bit port = BE[3:0]
3 The TW cycles are present when the WAIT field is set to 2 or more.
4 The TA* and TEA*/LAST signals are for reference only.
38
NS7520 Datasheet 03/2006