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80-0206-R Datasheet, PDF (9/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor | |||
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Data Sheet
RSC-4128
Using the RSC-4128
Creating applications using the RSC-4128 requires the development of electronic circuitry, software code, and
speech/music data files. Software code for the RSC-4128 can be developed using a complete suite of RSC-4128
development tools including In-Circuit Emulator, C Compiler, and âpush buttonâ tools for speech recognition and
synthesis data files. Sensory provides free design reviews of customer applications to assist in the speech dialog
and speech I/O design. Sensory also offers application development services. For more information about
development tools and services, please contact Sensory.
When using the RSC-4128 macro blocks such as the AFE, digital filters, L1, etc, for purposes other than as
intended in the FluentChip⢠technology modules, in applications that will also use FluentChip⢠technologies, care
must be taken to avoid conflicts that may cause adverse impact on functionality. Contact Sensory Technical
Support for help in avoiding these conflicts.
Instruction Set
The instruction set for the RSC-4128 has 60 instructions comprising 13 move, 7 rotate, 11 branch, 22 arithmetic,
and 7 miscellaneous instructions. All instructions are 3 bytes or fewer and no instruction requires more than 10
clock cycles (plus wait states) to execute. (see âInstruction Set Opcodes and Timing Detailsâ for detailed
descriptions)
Flags
The âflagsâ register (register FF) has bits that are set/cleared by arithmetic/logical instructions, a trap enable bit set
under program control, a read-only stack overflow bit cleared at power on and set by stack wrap around, and the
Global Interrupt Enable bit:
0FFH
R/W
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 3:
Bit 1:
Bit 0:
âflagsâ
carry
zero
sign
trap
stkoflo
stkfull
(unused)
gie
(set = 1 when result of arith/log instruction is 0)
(set = 1 when result of arith/log instruction has msb high)
(read-only, initialized to 0, set to 1 on stack overflow)
(read-only, initialized to 0, set to 1 on stack full)
(Global Interrupt Enable)
NOTE: The âtrapâ bit must be left written as â0â.
Flags Hold
The âflagsHoldâ register (register CF) stores the âflagsâ value when an interrupt occurs. Unlike previous RSC chips,
the RSC-4128 processor has read/write access to âflagsHoldâ for multi-tasking purposes. Since the âflagsâ register
is restored from the âflagsHoldâ register upon return from interrupt, the âstkofloâ and âstkfullâ bits are omitted from
the âflagsHoldâ register to prevent inadvertent clearing of these bits.
0CFH
R/W
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
âflagsHoldâ
carry
zero
sign
trap
(unused â reads 0)
(unused â reads 0)
(unused â reads 0)
gie
NOTE: The âtrapâ bit must be left written as â0â.
See the discussion in âInterruptsâ section relating to the value of âgieâ stored in the âflagsHoldâ register when an
interrupt occurs during execution of an instruction that clears the âgieâ bit.
9
P/N 80-0206-R
© 2006 Sensory Inc.
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