80-0206-R Datasheet, PDF (20/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

RSC-4128
Data Sheet
OSC1
OSC1 is enabled by programming register E8.Bit0 to “0”, which is the reset state for this bit. This bit is also
programmed to “0” during a Wakeup Event, enabling OSC1, if register E8.Bit2 is programmed to “0”. (see “Power
and Wakeup Control” section) In this case, a 10-20 millisecond delay will be forced to allow OSC1 to reach stable
oscillation. OSC1 must run at 3.58 MHz when using the FluentChip™ technologies, but may be slower if the RSC-
4128 is used as a general purpose platform for other applications. When OSC1 is disabled, the PLL which
generates the 14.32MHz clock (CLK1) is also disabled.
OSC2
OSC2 is enabled by programming register E8.Bit1 to “1”. The reset state for this bit is “0”, so this oscillator is
disabled by reset. OSC2 will be enabled during a Wakeup Event if register E8.Bit2 is programmed to “1”. (see
“Power and Wakeup Control” section) No delay will be forced, as OSC2 is assumed to be running during Idle
mode. The OSC2 source may be set to an external 32 KHz crystal by programming register EF.Bit2 to “0” (Note:
register EF.Bit7 must be “0” to enable writing EF.Bit2) The external 32KHz crystal should be used when accurate
timing and/or time-keeping is essential. In this mode, OSC2 is capable of achieving errors as low as 20ppm,
depending on the quality of the crystal and crystal circuit design. A typical value for the crystal bias capacitors is
27pF, but this will vary depending on the crystal quality and stray capacitance inherent in the application board
layout.
The OSC2 source may be set to an on-chip RC by programming register EF.Bit2 to “1” (Note: register EF.Bit7 must
be “0” to enable writing EF.Bit2). When using the on-chip RC, no external components are required for OSC1. The
on-chip RC value will vary due to process, temperature and supply voltage variations, so this oscillator frequency
will vary by +/- 30%. The on-chip RC mode should be used for low power modes where timing is not critical and
minimum system cost is important.
Oscillator Stabilization
When exiting Sleep mode (see “Power and Wakeup Control” section) OSC1 will have a forced 10-20millisecond
delay for stabilization if it is enabled. If OSC2 is enabled, it may require several seconds to stabilize, after which
the RSC4128 will begin running. Therefore, for fast response out of Sleep mode OSC1 should be enabled.
Clocks
The RSC-4128 uses a fully static core – the processor can be stopped (by removing the clock source) and
restarted without causing a reset or losing contents of internal registers. Dynamic operation is guaranteed from
~1KHz to 14.32 MHz.
Fast Clock
The 3.58 MHz OSC1 frequency is quadrupled by an on-chip PLL to produce a 14.32 MHz internal clock (CLK1).
Creating the internal clock in this way avoids an expensive high frequency crystal, substantially reducing overall
system cost. When used as the processor clock (see below), the 14.32 MHz internal clock creates internal RAM
cycles of 70 nsec duration, and internal or external Code/Data memory cycles of 140 nsec duration. Careful design
may allow operation with memories having access times as slow as 140 nsec.
Slow Clock
OSC2 generates an internal clock (CLK2) with an equivalent frequency to OSC2. When used as the processor
clock (see below), the RAM access cycles are one CLK2 cycle and Code/Data access cycles are two CLK2 cycles.
Processor Clock
Either CLK1 or CLK2 can be selected as the processor clock (PCLK) on the fly by changing the value of register
E8.Bit2. The reset state defaults to CLK1. (NOTE: it is possible to select a disabled clock as the processor clock. It
is the responsibility of the programmer not to select a clock until the corresponding oscillator has been enabled and
allowed to stabilize.) Power savings may result by using CLK2 when the processor is a lower activity mode and
using CLK1 when in a higher activity mode. If the use of an external clock driver is desired, the output of that driver
should be connected to the XI1 pin.
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P/N 80-0206-R
© 2006 Sensory Inc.