80-0206-R Datasheet, PDF (10/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

RSC-4128
Data Sheet
ERRATA NOTE: “Shadowing” of the “gie” flag bit in the flagsHold register is not disabled during an Interrupt
Service Routine (ISR) as intended, due to design errata. Therefore, any operation that directly modifies the flags
register “gie” bit (mov, logic operations, arithmetic operations, CLI, STI, etc directly on the flags register) will
erroneously invoke a “shadowing” of the flags register “gie” bit in the flagsHold register.
To avoid this problem, simply store the flagsHold register in a temporary location immediately upon entering an ISR
and restore the flagsHold register from that temporary location as the final instruction before exiting the ISR.
Stack
There is a 16-level, 16-bit stack for saving the program counter for subroutine calls and interrupt requests. The
stack pointer wraps around on overflow or underflow. When the stack read and write pointers indicate that stack
overflow has occurred, the “stkoflo” bit in the “flags” register is set. Once set, this bit can only be cleared by a
processor reset. The bit may be tested by software, but it performs no other function. When the stack read and
write pointers indicate that stack is full, the “stkfull” bit in the “flags” register is set. This bit will be reset once the
stack is not full.
Stack Pointers
The 16-level stack has two 4-bit pointers, stack write and stack read. They are normally written by the processor
upon execution of a “CALL” instruction or an interrupt.
The stack also has a 6-bit index register “stkNdx” (register F6) and an 8-bit data port register “stkData” (register F7)
that are used to access the stack contents as bytes in a register file under program control. The contents of the
stack location selected by the “stkNdx” register may be read or written by the processor via MOV instructions at the
“stkData” register. The stack register index must be written first, then the stack data can be read.
The Stack read and write pointers (4 bits each) are also mapped to addresses accessible via the Stack Register
Index.
Stack contents accessed by value in stack register index (“stkNdx”, register F6)
00H Stack0 Lo
08H Stack4 Lo
10H Stack8 Lo
18H
01H Stack0 Hi
09H Stack4 Hi
11H Stack8 Hi
19H
02H Stack1 Lo
0AH Stack5 Lo
12H Stack9 Lo
1AH
03H Stack1 Hi
0BH Stack5 Hi
13H Stack9 Hi
1BH
04H Stack2 Lo
0CH Stack6 Lo
14H StackA Lo
1CH
05H Stack2 Hi
0DH Stack6 Hi
15H StackA Hi
1DH
06H Stack3 Lo
0EH Stack7 Lo
16H StackB Lo
1EH
07H Stack3 Hi
0FH Stack7 Hi
17H StackB Hi
1FH
20- (unused)
30- (unused)
3EH StackWritePtr 3FH
2FH
3DH
(4bits only)
StackC Lo
StackC Hi
StackD Lo
StackD Hi
StackE Lo
StackE Hi
StackF Lo
StacKF Hi
StackReadPtr
(4bits only)
Register and User RAM
The RSC-4128 has a physical register RAM space of 896 bytes. There is an additional RAM space of 64 bytes
dedicated to Special Function Registers (SFRs), for a total register RAM space of 960 bytes. User RAM is
assigned 262 bytes of this register RAM space, as detailed below.
Logical register space addressing is architecturally limited to 8 bits (256 bytes). Therefore a banking scheme is
used to provide the total of 960 bytes of register RAM space. The lower 128 bytes and the top 64 bytes of
addressing are used to directly address register RAM. The remaining 64 bytes (080H-0BFH) are banked to provide
the remaining 768 bytes of register RAM space. This 768 bytes of register RAM is divided into 12 banks of 64
bytes each. The “bank” register (register FC) is combined with logical addressing to access these 12 banks. Here
is a table illustrating the breakdown of register RAM space:
000H-07FH
080H-0BFH
0C0H-0FFH
unbanked register RAM
banked register RAM
unbanked register RAM (SFRs)
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P/N 80-0206-R
© 2006 Sensory Inc.