80-0206-R Datasheet, PDF (12/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

RSC-4128
Data Sheet
Combined with OSC2, Timer2 and an active microphone, the total current consumed in Idle with Audio Wakeup
mode is about 150 microamps.
Sleep mode is entered by setting register E8.Bit7=1 (“ckCtl” register; “pdn” bit), register E8.Bit0=1 (“osc1_off”) and
register E8.Bit1=0 (OSC2 off). Idle mode is entered by setting register E8.Bit7=1, register E8.Bit1=1 (“osc2_on”)
and register E8.Bit0=1. Setting register E8.Bit7=1 (“pdn”) freezes the processor, but does not insure that the DAC,
Audio Wakeup, and the PWM are placed in the lowest possible current-consumption state. Software control must
power these blocks down prior to setting “pdn” to “1”, according to the procedures indicated in “DAC”, “Audio
Wakeup”, and “Pulse Width Modulator Analog Output” Sections. The “FluentChip™ Technology Library Manual”
provides sample code for achieving the lowest current-consumption state for Sleep and Idle modes. The state of
“pdn” bit may be observed externally on the PDN pin (see pin definitions in “Package Options” section) and used to
control power down of circuitry external to the RSC-4128, if desired.
NOTE: GPIO (Ports 0,1 & 2) should be put in input mode and a known state (e.g. light pull-up) whenever practical
to conserve power and not in conflict with their intended function, and especially in powerdown mode to achieve the
specified minimum supply current consumption. The external memory interface (A[19:0], D[7:0], -RDR, -WRC, -
RDF and –WRD) automatically goes into a high-Z state and is pulled up by a 100 Kohm internal resistor when the
“pdn” bit is set, to conserve current.
Register E8 contains both the “pdn” bit and the processor clock selector (Bit2). The clock selector bit determines
whether the 14.32 clock (“fast clock”) or the 32KHz clock (“slow clock”) will be used at wakeup time, independent of
what clock rate was being used before or during power down mode. This allows the processor clock after wakeup
to be the same or different from the processor clock used when the power-down flag was set. (see “Clock” section
for complete explanation)
To minimize power consumption, most operational blocks on the chip also have individual power controls that may
be selectively enabled or disabled by the programmer.
Wakeup from powerdown
During a Wakeup event the processor, which was "frozen" when register E8.Bit7 was set, will be restarted without
loss of context. Note that a Wakeup event does not cause a reset. A reset of the chip will also cancel a power
down mode, but with a corresponding loss of processor context.
Wakeup events terminate a power-down state. In Sleep mode, only an I/O Wakeup event can initiate a wake-up. In
Idle mode, an Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wakeup.
An I/O Wakeup is an edge triggered event, enabled by setting the bit(s) high in registers E9 or EA corresponding to
the desired I/O pin(s) to be used for wakeup. E9 controls P0 wakeup enable and EA controls P1 wakeup enable.
The polarity of the edge causing the Wakeup event is controlled by putting the appropriate port pin in input mode
and writing the appropriate bit in the output register for that pin to the desired polarity – a “1” for a positive going
edge and a “0” for a negative going edge. (see “General Purpose I/O” section for complete explanation) When the
edge on the Wakeup pin matches the polarity assigned in the output register, a Wakeup will occur.
A T2 Wakeup is enabled by setting register E8.Bit6 high. Then an overflow of timer T2 will generate an interrupt
request, which in turn will trigger a wakeup event. Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared
prior to powering down to allow the wakeup interrupt request to occur. (the “Timers/Counters” section describes
how timer T2 is configured)
An Audio Wakeup is generated by special circuitry that can detect several classes of sounds, even while in low
power mode. When the class of sound selected by the programmer is detected by this circuitry a wakeup event will
occur. (see the “Audio Wakeup” section for more information)
General Purpose I/O
The RSC-4128 has 24 general-purpose I/O pins (P0.0-P0.7, P1.0-P1.7, P2.0-P2.7). Each pin can be programmed
as an input with weak pull-up (~200kΩ equivalent device); input with strong pull-up (~10kΩ equivalent device); input
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P/N 80-0206-R
© 2006 Sensory Inc.