80-0206-R Datasheet, PDF (18/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

RSC-4128
Data Sheet
Access of external ROM space is always controlled by these wait state bits. Internal ROM space and all external
R/W space accesses may also controlled by these bits, unless otherwise selected by bits in the clock extension
register (register D6, “clkExt”) The internal RAMs always operate with zero wait states.
Register D6 provides for extended control of some clocks derived from OSC1 for producing additional timer scaling
or specialized wait states. When Bit 5 is set, it overrides the “bank” register control of wait states during MOVX
instructions which access external read/write memory (register D2.Bit4=1), and forces a fixed value of 4 wait states
(nominal 350ns access). When Bit 7 is set, it overrides the “bank” register control of wait states during internal
ROM accesses and forces zero wait states. Using these controls, various memory access speeds may be
accommodated within one application.
Bit 5
0: Certain MOVX* instructions use the Wait State divisor in register FC.Bits[7:5]
1:Certain MOVX* use fixed 4 Wait States (nominal 350nsec access)
Cleared by reset
Bit 6
0: MT timer clock is disabled
1: MT timer clock I s enabled
Cleared by reset
Bit 7
0: Accesses to internal ROM use the Wait State divisor set in register 0FCh[7:5]
1: Accesses to internal ROM use selected CLK (no wait states)
Cleared by reset.
* MOVX accessing external read-write memory (“rw”; register D2.Bit4=1).
Instruction Opcode Operand 1 Operand 2 Description
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
POP
PUSH
MOVY
MOVY
MOVD
10 dest
Source
register to register
11 @dest
Source
register to register-indirect
12 dest
@source register-indirect to register
13 dest
#immed immediate data to register
14 dest
@source code space to register
15 @dest
Source
register to code space
16 dest
@source data space to register
17 @dest
Source
register to data space
18 dest
@++source register to register data
stack pop (source pre-
incremented)
19 @dest--
Source
register to register data
stack push (dest post-
decremented)
1A dest
@source RAMY to register, indirect
1B @dest
source
register to RAMY, indirect
1C dest_pair source_pair register to register, direct,
16-bit MOV
Bytes
3
3
3
3
3
3
3
3
3
3
3
3
3
Cycles
5
5
6
4
7
8
7
8
10
9
7
7
7
+Cycles/
Waitstate
3
3
3
3
4
4
4*
4*
3
3
3
3
3
*MOVX instructions will have the number of wait states selected by register FC.Bits[7:5], unless register D2.Bit4
and register D6.Bit5 are set, in which case the number of wait states is fixed at 4.
18
P/N 80-0206-R
© 2006 Sensory Inc.