80-0206-R Datasheet, PDF (25/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

Data Sheet
RSC-4128
If an “irq” bit is set high and the corresponding “imr” bit is set high and the Global Interrupt Enable (“gie”; register
FF.bit0) bit is set high, an interrupt will occur. Interrupts may be nested if software handles saving and restoring the
“flagsHold” register (register CF). The “flags” register is copied to the “flagsHold” register and then the Global
Interrupt Enable is cleared, preventing subsequent interrupts until the IRET instruction is executed. The IRET
instruction will restore the “flags” register from the “flagsHold” register. The Global Interrupt Enable bit in the “flags”
register must not be re-enabled during the period after an interrupt has been acknowledged and before an IRET
instruction has been executed unless interrupt nesting is desired.
If an interrupt occurs during an instruction that clears the Global Interrupt Enable bit (typically the CLI instruction)
the value of the “gie” bit will be 0 upon completion of the Interrupt Service Routine and Return From Interrupt to the
instruction following the one that cleared the “gie” bit. (NOTE: This is a change from the operation of the RSC-364.)
ERRATA NOTE: “Shadowing” of the “gie” flag bit in the flagsHold register is not disabled during an Interrupt
Service Routine (ISR) as intended, due to design errata. Therefore, any operation that directly modifies the flags
register “gie” bit (mov, logic operations, arithmetic operations, CLI, STI, etc directly on the flags register) will
erroneously invoke a “shadowing” of the flags register “gie” bit in the flagsHold register.
To avoid this problem, simply store the flagsHold register in a temporary location immediately upon entering an ISR
and restore the flagsHold register from that temporary location as the final instruction before returning from the ISR.
The “flagsHold” register is accessible under program control at address CF in order to improve multi-tasking
operation.
External interrupts may be enabled on pins P0.0 (1^st external interrupt request) and P0.2 (2^nd external interrupt
request), by setting register FD.Bit3=1 and register FD.Bit6=1, respectively. The polarity of the edges to trigger an
external interrupt request for P0.0 and are controlled by register D5.Bits[1:0]. Setting D5.Bit0=0 will cause a
positive going edge on P0.0 to generate and interrupt and D5.Bit0=1 will cause a negative going edge to generate
an interrupt. The same controls for P0.2 are possible with D5.Bit1. The corresponding external “irq” flag will be set
if the transition matches the interrupt edge control bit.
NOTE: If P0.0 or P0.2 are configured as outputs, writing to those outputs can trigger external interrupt requests if
the proper edge polarities occur. The user must be careful to avoid this, unless it is intended to use this as a way of
generating interrupt requests under internal software control.
An interrupt is disabled by writing a zero to the corresponding bit in the imr register (register 0FDH). However, an
active interrupt request can still be pending. To be certain that an interrupt does not happen, you should clear the
interrupt request flag in the irq register (register 0FEH) as well. For example:
; Disable timer 1 interrupt
cli
and imr,#0FEH
mov irq,#0FEH
sti
; mask new interrupt requests
; clear any pending interrupt request
For each interrupt, execution begins at a different address:
Interrupt #0
Interrupt #1
Interrupt #2
Interrupt #3
Interrupt #4
Interrupt #5
Interrupt#6
Interrupt#7
Address 04H
Address 08H
Address 0CH
Address 10H
Address 14H
Address 18H
Address 1CH
Address 20H
(Overflow of Timer 1)
(Overflow of Timer 2)
(Filter End Marker)(Reserved for Technology code)
(Edge of P00)
(Overflow of Timer 3)
(Block End)(Reserved for Technology code)
(Edge of P02)
(Overflow of MT timer)
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P/N 80-0206-R
© 2006 Sensory Inc.