80-0206-R Datasheet, PDF (21/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

Data Sheet
RSC-4128
After source selection, the processor clock can be divided-down in order to limit power consumption. Register
E8.Bits 4 and 3 determine the divisor:
E8.Bit4
0
0
1
1
E8.Bit3
0
1
0
1
Processor Clock Divisor
1/2
1/1 (reset default)
1/8
1/256
A Processor Clock divisor of 1/1 is typically required for FluentChip™ technology.
The processor clock is gated by the Wake-up delay and also gated by “pdn”=0 (register E8.Bit7), in such a way that
the processor is stopped in a zero-power state with no loss of context.
Other System Clocks
The following functional clocks are generated from OSC1: CLK1, the digital filter clock, the analog front end (AFE)
master clock, the L1 clock, Timer1 clock, Timer3 clock, and the Multi-Task timer clock. The Timer2 clock and the
Watchdog timer clock are generated from OSC2. (see each block’s section for clocking details) All clocks except
the Timer2 and Audio Wakeup clocks are gated with the pdn = 0, to assure they are disabled during IDLE and
SLEEP modes. Timer2 and Audio Wakeup can run during Idle mode to produce a T2 Wakeup or Audio Wakeup.
(see “Power and Wakeup Control” section)
Timers/Counters
Four programmable timers and one fixed timer in the RSC-4128 provide a variety of timing/counting options. Timers
1, 2, 3 and the Multi-Tasking timer can all generate interrupts upon overflow. (See “Interrupts” section)
Timers 1 and 3
Each of Timer1 (T1) and Timer3 (T3) consists of an 8-bit reload value register, an 8-bit up-counter, and a 4-bit
decoded prescaler register. Each is clocked by CLK1 divided by 16. The reload register is readable and writeable
by the processor. The counter is readable with precaution taken against a counter change in the middle of a read.
NOTE: If the processor writes to the counter, the data is ignored. Instead, the act of writing to the counter causes
the counter to preset to the reload register value.
When the timer overflows from FFH, a pulse is generated that sets register FE.Bit 0 (“irq” register; T1 bit) or register
FE. Bit 4(T3 bit). The width of the pulse is the pre-scaled counter clock period. Instead of overflowing to 00, the
counter is automatically reloaded on each overflow.
For example, if the reload value is 0FAH, the counter will count as follows:
0FAH, 0FBH, 0FCH, 0FDH, 0FEH, 0FFH, 0FAH, 0FBH etc.
The overflow pulse is generated during the period after the counter value reaches 0FFH.
A separate 4-bit decoded prescaler register is between the clock source and the up-counter for each of T1 and T3.
The 4bits represent the power of 2 used to divide the timer clock before applying it to the up-counter. For example,
a prescaler value of 0 passes the timer clock directly through (divides by 2^0 = 1). A prescaler value of 5 divides the
timer clock by 2^5 = 32.
21
P/N 80-0206-R
© 2006 Sensory Inc.