80-0206-R Datasheet, PDF (13/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

Data Sheet
RSC-4128
without pull-up, or as an output with sufficient drive to light an LED. (See “DC Characteristics” section for I/O
electrical characteristics.) This is accomplished by programming combinations of 48 bits of configuration registers
assigned to the I/O pins.
Two control registers, A and B, are used to control the nature of inputs and outputs for each port. Registers E6
(“p0CtlA”) and E7 (“p0CtlB”), E2 (“p1CtlA”) and E3 (“p1CtlB”), and DE (“p2CtlA”) and DF (“p2CtlB”), are the control
registers A and B for ports P0, P1 and P2, respectively. Each port pin’s I/O configuration may be controlled
independently by the state of it’s corresponding bits in these registers. Control registers A and B together
determine the function of the port pins as follows:
B bit A bit Port Pin Function
0
0
Input - Weak Pull-up
0
1
Input - Strong Pull-up
1
0
Input - No pull-up
1
1
Output
(For example, if register E7.Bit 4 is set high, and register E6.Bit 4 is low, then pin P0.4 is an input without a pull-up
device.)
After reset, pins P0.0-P0.7, P1.0-P1.7, and P2.5-P2.7 are set to be digital inputs with weak pull-ups, and pins P2.0-
P2.4 are configured as analog input pins with no pull-ups. Being reset as an input and lightly pulled to a known
(high) state ensures minimum power consumption as a default beginning. Sixteen of these pins (Ports P0 and P1)
can also be configured as inputs to control IO Wakeup events. (see “Power and Wakeup Control” section).
P2.0, P2.1, P2.3, and P2.4 can be configured as comparator inputs. P2.2 can be configured as a comparator
reference. Some or all of P2.0-P2.4 can be configured as digital inputs by the use of the “cmpCtl” register (register
D4) Bits[2:0] (see “Comparator Unit” section)
Note: When configuring P2.0-P2.4 as digital inputs the associated weak pull-up should be selected as shown
above.
P0.0 and P0.2 can be configured as External Interrupts (see “Interrupts” section). P0.1 can be configured in input
mode as a gate for an external event counter. (See “Timers/Counters” Section)
Registers E5 (“p0In”) and E4 (“p0Out”), E1(“p1In”) and E0 (“p1Out”), and DD (“p2In”) and DC (“p2Out”), provide
paths for data input and data output on P0, P1 and P2, respectively. The port input registers (E5, E1 and DD) are
actually buffers which record the value at the ports at the time they are read. The port output registers (E4, E0 and
DC) latch the data written to them and express it on the ports when the ports are configured as an output.
Following is a summary of the general purpose I/O control registers:
Register
0DCH Read/Write
0DDH Read
0DEH Read/Write
0DFH Read/Write
0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E6H
0E7H
Read/Write
Read
Read/Write
Read/Write
Read/Write
Read
Read/Write
Read/Write
P2[0:7] (port 2) output register. Cleared by reset.
Port 2 input.
Port 2 Control Register A. Cleared by reset.
Port 2 Control Register B. Bits[7:5] cleared by reset.
Bits[4:0] set by reset
P1[0:7] (port 1) output register. Cleared by reset.
Port 1 input.
Port 1 Control Register A. Cleared by reset.
Port 1 Control Register B. Cleared by reset.
P0[0:7] (port 0) output register. Cleared by reset.
Port 0 input.
Port 0 Control Register A. Cleared by reset.
Port 0 Control Register B. Cleared by reset.
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P/N 80-0206-R
© 2006 Sensory Inc.