80-0206-R Datasheet, PDF (24/49 Pages) List of Unclassifed Manufacturers – Speech Recognition Processor

RSC-4128
Data Sheet
Executing the WDC instruction clears the WDT counter, sets register FB.Bit4=1, clears register FB.Bit5=0
(wd_timed-out), and starts a new timeout period. The OSC2 oscillator may also be enabled by executing the WDC
instruction. If the oscillator is stopped, executing this instruction also sets register E8.Bit1=1 to enable OSC2. In this
case, timing will not begin until the oscillator is active.
Once the WDT is started, software must execute the WDC instruction at a rate faster than the timeout period.
Otherwise the watchdog circuit sets the “watch dog timed out” bit (register FB.Bit5) and generates a Timed Out
Reset, which resets the RSC-4128. A Timed Out Reset disables the WDT. (See “Reset” section) Software in the
reset routine can detect that the WDT timed out (FB.Bit5=1), since that is preserved during the Timed Out Reset.
Placing the chip in Sleep or Idle mode disables the WDT operation.
Timer Powerdown
Some timers have independent power down control, while others may only be powered down by turning off their
clock source, setting the “pdn” bit, or resetting. It is not required for the application to do this for full chip power
down, as long as it complies with directions in the “Power and Wakeup Control” section. However, one may
choose to reduce power consumption in active mode by turning off individual timers.
Timer 3 and MT Timer may be independently powered down by setting the register D9.Bit 7 to “0” (“t3Ctl” register,
“t3_on” bit) and register D6.Bit 6 to “0” (“clkExt” register, “MTclk_on” bit), respectively.
Timer 1, Timer 2 and the WDT require special circumstances to powerdown, which are appropriate for their
application. See their respective descriptions for more detail.
Interrupts
The RSC-4128 allows for 8 interrupt request sources, as selected by software. All are asynchronous positive edge
activated except the two external requests, which have programmable edges. Each has its own mask bit and
request bit in the “imr” and “irq” registers respectively. There is a Global Interrupt Enable flag in the “flags”
registers. The “imr” and “irq” bits are listed below with the RSC-4128 interrupt source shown in parenthesis:
0FDH “imr”
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
1= enable interrupt request #7 (Overflow of MT timer)
1= enable interrupt request #6 (Edge of P0.2)
1= enable interrupt request #5 (Block End)(Reserved for Technology code)
1= enable interrupt request #4 (Overflow of Timer3)
1= enable interrupt request #3 (Edge of P0.0)
1= enable interrupt request #2 (Filter End Marker)(Reserved for Technology code)
1= enable interrupt request #1 (Overflow of Timer2)
1= enable interrupt request #0 (Overflow of Timer1)
0FEH “irq”
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
1=interrupt request #7 (Overflow of MT Timer)
1= interrupt request #6 (Edge of P0.2)
1=interrupt request #5 (Block End)(Reserved for Technology code)
1= interrupt request #4 (Overflow of Timer3)
1= interrupt request #3 (Edge of P0.0)
1= interrupt request #2 (Filter End Marker)(Reserved for Technology code)
1= interrupt request #1 (Overflow of Timer2)
1= interrupt request #0 (Overflow of Timer1)
24
P/N 80-0206-R
© 2006 Sensory Inc.