CH7003B Datasheet, PDF (6/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
CH7003B
Digital Video Interface
The CH7003 digital video interface provides a flexible digital interface between a computer graphics controller and
the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital
interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control
through the CH7003 register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either
multiplexed mode or 16-bit input operation in de-multiplexed mode. It will also accept either YCrCb or RGB (15,
16 or 24-bit) data formats. A summary of the data format modes is as follows:
Table 2. Input Data Formats
Bus Width
16-bit
15-bit
16-bit
8-bit
8-bit
8-bit
8-bit
12-bit
12-bit
16-bit
Transfer Mode
Non-multiplexed
Non-multiplexed
Non-multiplexed
2X-multiplexed
2X-multiplexed
3X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
Color Space and Depth
RGB 16-bit
RGB 15-bit
YCrCb (24-bit)
RGB 15-bit
RGB 16-bit
RGB 24-bit
YCrCb (24-bit)
RGB 24
RGB 24
RGB 24 (32)
Format Reference
5-6-5 each word
5-5-5 each word
CbY0,CrY1...(CCIR656 style)
5-5-5 over two bytes
5-6-5 over two bytes
8-8-8 over three bytes
Cb,Y0,Cr,Y1,(CCIR656 style)
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
8-8,8X over two words
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7003 can operate in either master (the CH7003 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
ouput format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or
3X the pixel data rate (subject to a 100 MHz frequency limitation). In the case of a 1X pixel clock the CH7003 will
automatically use both clock edges if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7003. In the case of CCIR656 style input, embedded sync may also be used. In
each case, the horizontal timing signal (horizontal sync) must be derived from the pixel clock, with the period set to
exactly 8 times (9 times for 720x400 modes) the pixel clock period, times an integer value. Each line to be set, is set
up by the leading edge of Horizontal sync. The vertical timing signal must be able to be set to any integer number of
lines between 420 and 836.
Master Clock Mode: The CH7003 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock
signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the
pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC
transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet
the specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after
the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count),
plus horizontal sync width, will determine when the chip will begin to sample pixels.
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201-0000-023 Rev.4.1, 8/2/99