CH7003B Datasheet, PDF (33/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
Register Descriptions (continued)
Table 20. Luma Filter Bandwidth
YCV
0
1
YSV[1:0]
00
01
10
11
YPEAK
0
1
Luma Composite Video Filter Adjust
Low bandwidth
High bandwidth
Luma S-Video Filter Adjust
Low bandwidth
Medium bandwidth
High bandwidth
Reserved (decode this and handle the same as 10)
Disables the Y-peaking circuit
Disables the peaking filter in luma S-Video channel
Enables the peaking filter in luma S-Video channel
CH7003B
Table 21. Chroma Filter Bandwidth
CBW[1:0]
00
01
10
11
Chroma Filter Adjust
Low bandwidth
Medium bandwidth
Med-high bandwidth
High bandwidth
• Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A "1"
in this location enables the output of a black and white image on composite, thereby eliminating the degrading
effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high
accuracy.
• Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF
to one causes a five line flicker filter to be used. The default setting of zero uses a four line flicker filter.
Input Data Format Register
Bit:
7
Symbol:
Type:
Default:
6
DACG
R/W
0
5
4
RGBBP
R/W
0
Symbol: IDF
Address: 04H
Bits: 6
3
IDF3
R/W
0
2
IDF2
R/W
0
1
IDF1
R/W
0
0
IDF0
R/W
0
This register sets the variables required to define the incoming pixel data stream, including data format and input bit
width, and VBI encoding.
201-0000-023 Rev 4.1, 8/2/99
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