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CH7003B Datasheet, PDF (41/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder
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CHRONTEL
CH7003B
Register Descriptions (continued)
PLL N Value Register
Symbol: PLLN
Address: 15H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol: N7
N6
N5
N4
N3
N2
N1
N0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default: 1
0
0
0
0
0
0
0
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7003 is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is
always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a
master and pseudo-master modes is calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)]
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below.
Table 26. M and N Values for Each Mode
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
VGA Resolution, TV
Standard, Scaling Ratio
512X384, PAL, 5:4
512X384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640X400, NTSC, 1:1
640X400, NTSC, 7:8
N 10-
bits
20
9
126
110
53
339
106
70
108
9
94
22
190
M 9-
bits
13
4
89
63
26
138
63
33
61
3
63
11
89
Mode
13
14
15
16
17
18
19
20
21
22
23
24
VGA Resolution, TV
Standard, Scaling Ratio
640X480, PAL, 5:4
640X480, PAL, 1:1
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
N 10-
bits
20
9
9
110
126
190
647
86
284
94
62
302
M 9-bits
13
4
3
63
63
89
313
33
103
33
19
89
Buffered Clock Output Register
Bit:
7
6
5
Symbol:
SHF2
Type:
R/W
Default:
0
4
SHF1
R/W
0
3
SHF0
R/W
0
2
SCO2
R/W
0
Symbol: BCO
Address: 17H
Bits: 5
1
SCO1
R/W
0
0
SCO0
R/W
0
The buffered clock output register determines which clock is selected to be output at the buffered clock output pin,
and what frequency value should be output if a VCO derived signal is output. The tables below show the possible
output signals.
201-0000-023 Rev 4.1, 8/2/99
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