CH7003B Datasheet, PDF (35/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
Register Descriptions (continued)
Table 23. Clock Modes
XCM[1:0]
00
00
00
01
01
01
1X
1X
1X
PCM[1:0]
00
01
1X
00
01
1X
00
01
1X
XCLK
1X
1X
1X
2X
2X
2X
3X
3X
3X
P-OUT
1X
2X
3X
1X
2X
3X
1X
2X
3X
Input Data Modes Supported
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
6
6
6
CH7003B
The Clock Mode Register also contains the following bits:
• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
negative edge, one selects the positive edge.
• Bit 5 Unused
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
14.31818MHz clock is used as a frequency reference, and the display mode register is decoded to determine
the PLL divider settings. In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided
by the value specified by XCM[1:0]. The divide by N is forced to one.
• Bit 7 (CFRB) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Bit:
Symbol:
Type:
Default:
7
SAV7
R/W
0
6
SAV6
R/W
0
5
SAV5
R/W
0
4
SAV4
R/W
0
3
SAV3
R/W
0
2
SAV2
R/W
0
Symbol: SAV
Address: 07H
Bits: 8
1
SAV1
R/W
0
0
SAV0
R/W
0
This register sets the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The
entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position
overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0
and active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading
edge of sync to the first active data must be a multiple of three clocks.
201-0000-023 Rev 4.1, 8/2/99
35