CH7003B Datasheet, PDF (46/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
CH7003B
Register Descriptions (continued)
CIV Control Register
Symbol: CIVC
Address: 21H
Bits: 3
Bit:
7
6
5
4
3
2
1
0
Symbol:
CIVH1
CIVH0
ACIV
Type:
R/W
R/W
R/W
Default:
0
0
1
The following controls are available through the CIV control register:
ACIV
1,
When the automatic calculated increment value is 1, the number calculated and present at the CIV
registers will automatically be used as the increment value for subcarrier generation, removing the
need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to
the subcarrier generation must be forced to free-run mode.
CIVH[1:0] These bits control the hysteresis circuit which is used to calculate the CIV value.
Calculated Increment Value Register
Symbol: CIV
Address: 22H - 24H
Bits: 8 each
Bit:
Symbol:
Type:
Default:
7
CIV#
R
0
6
CIV#
R
0
5
CIV#
R
0
4
CIV#
R
0
3
CIV#
R
0
2
CIV#
R
0
1
CIV#
R
0
0
CIV#
R
0
The CIV registers 22H through 24H, toghether with 2 bits from register 2H, define a 24-bit value, which is the
calculated increment value that should be used as the upper 24 bits of FSCI. This value is determined by a
comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the
following:
Register
22H
23H
24H
Contents
CIV[23:16]
CIV[15:8]
CIV[7:0]
Version ID Register
Symbol: VID
Address: 25H
Bits: 5
Bit:
7
6
5
4
3
2
1
0
Symbol: ^N/A
N/A
N/A
VID4
VID3
VID2
VID1
VID0
Type:
R
R
R
R
R
R
R
R
Default: ⁰
0
0
0
0
0
1
0
This read-only register contains a 5-bit value indicating the identification number assigned to this version of the
CH7003. The default value shown is pre-programmed into this chip and is useful for checking for the correct
version of this chip, before proceeding with its programming.
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