CH7003B Datasheet, PDF (40/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
Register Descriptions (continued)
CH7003B
256
224
192
160
128
96
64
32
0
0 32 64 96 128 160 192 224 256
Figure 26: Luma Transfer Function at different contrast enhancement settings
PLL Overflow Register
Symbol: MNE
Address: 13H
Bits: 5
Bit:
7
6
5
4
3
2
1
0
Symbol:
Reserved Reserved N9
N8
M8
Type:
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
The PLL Overflow Register contains the MSB bits for the ‘M’ and ‘N’ values, which will be described in the PLL-
M and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM
Address: 14H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol: ^M7
M6
M5
M4
M3
M2
M1
M0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default: ⁰
1
0
0
0
0
0
1
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7003 is operating in master or pseudo-master clock mode. In slave mode, an
external pixel clock is used instead of the frequency reference, and the division factor is determined by the
XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
40
201-0000-023 Rev.4.1, 8/2/99