CH7003B Datasheet, PDF (44/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
Register Descriptions (continued)
PLL Control Register
Bit:
7
6
5
4
3
Symbol:
PLLCPI
PLLCAP PLLS
Type:
R/W
R/W
R/W
Default:
0
0
1
CH7003B
2
PLL5VD
R/W
0
Symbol: PLLC
Address: 20H
Bits: 6
1
PLL5VA
R/W
1
0
MEM5V
R/W
0
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
PLLCAP
PLLCPI
MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the
memory supply is 3.3 volts.
PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is
used when the phase-locked loop analog supply is 3.3 volts.
PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when
the phase-locked loop digital supply is 3.3 volts (default).
PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL
supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL
supply) PLLS shold be 0, and five stages are used.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown in Table 30.
PLLCHI controls the charge pump current of the PLL. The default value of 0 should be used.
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201-0000-023 Rev.4.1, 8/2/99