CH7003B Datasheet, PDF (26/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
CH7003B
Transfer Protocols (continued)
AutoInc
Register Address Auto-Increment - to facilitate sequential R/W of registers.
AR[5:0]
“1”: Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be
incremented by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will automatically be incremented by one.
However, for the first read after an RAB, the Address Register will not be changed.
“0”: Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a
new RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will remain unchanged.
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7003. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc = 0,1.
CH7003 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7003 always acknowledges for writes (see Figure 21). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output
By Master-Transmitter
SD Data Output
By the CH7003
SC from
1
Master
Start
Condition
not acknowledge
acknowledge
2
8
9
clock pulse for
acknowledgement
Figure 21: Acknowledge on the Bus
Figure 22 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,
following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If
AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
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201-0000-023 Rev.4.1, 8/2/99