LM3S328 Datasheet, PDF (96/371 Pages) List of Unclassifed Manufacturers – Microcontroller

Internal Memory
7.2.2
7.2.2.1
7.2.2.2
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as:
0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000C
With the alias address calculated, an instruction performing a read/write to address 0x2202000C
allows direct access to only bit 3 of the byte at address 0x20001000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch
mechanism, protecting the contents of those blocks from being read by either the controller or by a
debugger.
Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via
the USec Reload (USECRL) register (see page 103).
On reset, USECRL is loaded with a value that configures the flash timing so that it works with the
default crystal value of 6 MHz. If software changes the system operating frequency, the new
operating frequency must be loaded into USECRL before any flash modifications are attempted.
For example, if the device is operating at a speed of 20 MHz, a value of 0x13 must be written to
the USECRL register.
Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in two 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block) in
the FMPPE (see page 102) and FMPRE registers (see page 101).
„ Flash Memory Protection Program Enable (FMPPE[Blockn:Block0]): If set, the block may
be programmed (written) or erased. If cleared, the block may not be changed.
„ Flash Memory Protection Read Enable (FMPRE[Blockn:Block0]): If set, the block may be
executed or read by software or debuggers. If cleared, the block may only be executed. The
contents of the memory block are prohibited from being accessed as data and traversing the
DCode bus.
96
April 27, 2007
Preliminary