LM3S328 Datasheet, PDF (247/371 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S328 Data Sheet
Bit/Field
4
3
2:0
Name
RXFE
BUSY
reserved
Type
RO
RO
RO
Reset
1
0
0
Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is
empty.
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit
remains set until the complete byte, including all stop bits, has
been sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
Reserved bits return an indeterminate value, and should never
be changed.
April 27, 2007
247
Preliminary