LM3S328 Datasheet, PDF (220/371 Pages) List of Unclassifed Manufacturers – Microcontroller

Analog-to-Digital Converter (ADC)
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2^AVG consecutive ADC samples at the
specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If
AVG is 6, 64 consecutive ADC samples are averaged to generate one result in the sequencer
FIFO. An AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Offset 0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
AVG
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2:0
Name
reserved
AVG
Type
RO
R/W
Reset
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Specifies the amount of hardware averaging that will be
applied to ADC samples. The AVG field can be any value
between 0 and 6. Entering a value of 7 creates unpredictable
results.
220
April 27, 2007
Preliminary