LM3S328 Datasheet, PDF (28/371 Pages) List of Unclassifed Manufacturers – Microcontroller

Architectural Overview
1.4.6.2
1.4.7
1.4.7.1
1.4.7.2
1.4.7.3
1.4.8
introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled
processor, certain regions in the memory map (SRAM and peripheral space) can use address
aliases to access individual bits in a single, atomic operation.
Flash (Section 7.2.2 on page 96)
The LM3S328 Flash controller supports 16 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of
code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
Additional Features
Memory Map (Section 3 on page 39)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S328 controller can be found on page 39. Register addresses are given as a hexadecimal
increment, relative to the module’s base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
JTAG TAP Controller (Section 5 on page 44)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is
implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions
select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The
multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for
the ARM, LMI, and unimplemented JTAG instructions.
System Control and Clocks (Section 6 on page 54)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
Hardware Details
Details on the pins and package can be found in the following sections:
„ Section 15, “Pin Diagram,” on page 340
„ Section 16, “Signal Tables,” on page 341
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April 27, 2007
Preliminary