LM3S328 Datasheet, PDF (279/371 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S328 Data Sheet
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of
SSIFSS causes the value contained in the bottom entry of the transmit FIFO to be transferred to
the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out
onto the SSITX pin. SSIFSS remains Low for the duration of the frame transmission. The SSIRX
pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSICLK. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is
driven onto the SSIRX line on the falling edge of SSICLK. The SSI in turn latches each bit on the
rising edge of SSICLK. At the end of the frame, for single transfers, the SSIFSS signal is pulled
High one clock period after the last bit has been latched in the receive serial shifter, which causes
the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSICLK
after the LSB has been latched by the receive shifter, or when the SSIFSS pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single
transfer. However, the SSIFSS line is continuously asserted (held Low) and transmission of data
occurs back-to-back. The control byte of the next frame follows directly after the LSB of the
received data from the current frame. Each of the received values is transferred from the receive
shifter on the falling edge of SSICLK, after the LSB of the frame has been latched into the SSI.
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
SSIRx
0 MSB
LSB
4 to 16 bits
output data
8-bit control
LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSICLK after SSIFSS has gone Low. Masters that drive a free-running SSICLK must ensure that
the SSIFSS signal has sufficient setup and hold margins with respect to the rising edge of
SSICLK.
Figure 13-12 illustrates these setup and hold time requirements. With respect to the SSICLK rising
edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFSS must have a
setup of at least two times the period of SSICLK on which the SSI operates. With respect to the
SSICLK rising edge previous to this edge, SSIFSS must have a hold of at least one SSICLK
period.
April 27, 2007
279
Preliminary