LM3S328 Datasheet, PDF (341/371 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S328 Data Sheet
16 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 129).
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
Table 16-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 16-2 lists the signals in alphabetical order by signal name. Table 16-3 groups the
signals by functionality, except for GPIOs. Table 16-4 lists the GPIO pins and their alternate
functionality.
Table 16-1. Signals by Pin Number (Sheet 1 of 3)
Pin
Number
Pin Name
1
ADC0
2
ADC1
3
ADC2
4
ADC3
5
RST
6
LDO
7
VDD
8
GND
9
OSC0
10
OSC1
11
PC7
CCP4
12
PC6
CCP3
13
PC5
CCP1
14
PC4
15
VDD
16
GND
17
PA0
U0Rx
Pin Buffer
Type Type
Description
I
Analog Analog-to-digital converter input 0.
I
Analog Analog-to-digital converter input 1.
I
Analog Analog-to-digital converter input 2.
I
Analog Analog-to-digital converter input 3.
I
TTL System reset input.
-
Power The low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or greater.
-
Power Positive supply for logic and I/O pins.
-
Power Ground reference for logic and I/O pins.
I
Analog Oscillator crystal input or an external clock reference input.
O Analog Oscillator crystal output.
I/O
TTL GPIO port C bit 7.
I/O
TTL Timer 2 capture input, compare output, or PWM output channel 4.
I/O
TTL GPIO port C bit 6.
I/O
TTL Timer 1 capture input, compare output, or PWM output channel 3.
I/O
TTL GPIO port C bit 5.
I/O
TTL Timer 0 capture input, compare output, or PWM output channel 1.
I/O
TTL GPIO port C bit 4.
-
Power Positive supply for logic and I/O pins.
-
Power Ground reference for logic and I/O pins.
I/O
TTL GPIO port A bit 0.
I
TTL UART0 receive data input.
April 27, 2007
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Preliminary