LM3S328 Datasheet, PDF (160/371 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR)
register and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change
takes effect at the next cycle after the write.
9.4 Register Map
Table 9-1 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that timer’s base address:
„ Timer0: 0x40030000
„ Timer1: 0x40031000
„ Timer2: 0x40032000
Table 9-2. GPTM Register Map
Offset Name
Reset
Type Description
0x000
0x004
0x008
0x00C
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
GPTMCFG
0x00000000
GPTMTAMR
0x00000000
GPTMTBMR
0x00000000
GPTMCTL
0x00000000
GPTMIMR
0x00000000
GPTMRIS
0x00000000
GPTMMIS
0x00000000
GPTMICR
GPTMTAILR
0x00000000
0x0000FFFF^a
0xFFFFFFFF
GPTMTBILR
GPTMTAMATCHR
0x0000FFFF
0x0000FFFF^a
0xFFFFFFFF
GPTMTBMATCHR 0x0000FFFF
GPTMTAPR
0x00000000
GPTMTBPR
0x00000000
GPTMTAPMR
0x00000000
GPTMTBPMR
0x00000000
R/W
R/W
R/W
R/W
R/W
RO
RO
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration
TimerA mode
TimerB mode
Control
Interrupt mask
Interrupt status
Masked interrupt status
Interrupt clear
TimerA interval load
TimerB interval load
TimerA match
TimerB match
TimerA prescale
TimerB prescale
TimerA prescale match
TimerB prescale match
See
page
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April 27, 2007
Preliminary