LM3S328 Datasheet, PDF (334/371 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
Bit/Field
1
Name
TREQ
0
RREQ
Write-Only Control Register
31:1
reserved
0
DA
Type
RO
RO
Reset
0
0
Description
This bit specifies the state of the I²C slave with regards to
outstanding transmit requests. If set, the I²C unit has been
addressed as a slave transmitter and uses clock
stretching to delay the master until data has been written
to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
Receive Request
This bit specifies the status of the I²C slave with regards
to outstanding receive requests. If set, the I²C unit has
outstanding receive data from the I²C master and uses
clock stretching to delay the master until the data has
been read from the I2CSDR register. Otherwise, no
receive data is outstanding.
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
WO
0
Device Active
1=Enables the I²C slave operation.
0=Disables the I²C slave operation.
334
April 27, 2007
Preliminary