W65C816S Datasheet, PDF (8/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
2 W65C816S FUNCTIONAL DESCRIPTION
W65C816S Data Sheet
The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02 in
applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages, including
full software compatibility with 6502 coding.
Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The Control
Section. Instructions obtained from program memory are executed by implementing a series of data transfers
within the Register Section. Signals that cause data transfers to be executed are generated within the Control
Section. The W65C816S has a 16-bit internal bus architecture with an 8-bit external data bus and 24-bit external
address bus.
2.1 Instruction Register (IR)
An Operation Code enters the processor on the Data Bus, and is latched into the Instruction Register during the
OpCode fetch cycle. This OpCode is then decoded, along with timing and interrupt signals, to generate various
Instruction Register control signals for use during instruction operations.
2.2 Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is executed. The TCU is set to zero each time
an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as is required to
complete the instruction. Each data transfer between registers depends upon decoding the contents of both the
Instruction Register and the Timing Control Unit.
2.3 Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the 16-bit ALU. In addition to data operations, the ALU also
calculates the effective address for relative and indexed addressing modes. The result of a data operation is stored
in either memory or an internal register. Carry, Negative, Overflow and Zero flags may be updated following the
ALU data operation.
2.4 Internal Registers (Refer to Programming Model Table 2-2)
2.5 Accumulator (A)
The Accumulator (A) is a general purpose register which contains one of the operands and the result of most
arithmetic and logical operations. In the Native mode (E=0), when the Accumulator Select Bit (M) equals zero,
the Accumulator is established as 16 bits wide (A, B=C). When the Accumulator Select Bit (M) equals one, the
Accumulator is 8 bits wide (A). In this case, the upper 8 bits (B) may be used for temporary storage in
conjunction with the Exchange Accumulator (XBA) instruction.
The Western Design Center
W65C816S
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