W65C816S Datasheet, PDF (21/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
Absolute -a
With Absolute (a) addressing the second and third bytes of the instruction form the low-order 16 bits of the
effective address. The Data Bank Register contains the high-order 8 bits of the operand address.
Instruction:
OpCode addrl addrh
Operand
DBR
addrh addrl
Absolute Indexed Indirect-(a,x)
With Absolute Indexed Indirect ((a,x)) addressing the second and third bytes of the instruction are added to the X
Index Register to form a 16-bit pointer in Bank 0. The contents of this pointer are loaded in the Program Counter
for the JMP instruction. The Program Bank Register is not changed.
Instruction:
OpCode
PBR
then:
PC = (address)
Abs olute Indexed with X-a,x
addrl addrh
addrh
addrl
X Reg
address
With Absolute Indexed with X (a,x) addressing the second and third bytes of the instruction are added to the X
Index Register to form the low-order 16-bits of the effective address. The Data Bank Register contains the
high-order 8 bits of the effective address.
Instruction:
Operand Address:
OpCode
addrl addrh
DBR
addrh addrl
+
X Reg
effective address
Absolute Indexed with Y-a,y
With Absolute Indexed with Y (a,y) addressing the second and third bytes of the instruction are added to the Y
Index Register to form the low-order 16-bits of the effective address. The Data Bank Register contains the
high-order 8 bits of the effective address.
Instruction:
Operand Address:
OpCode
addrl addrh
DBR
addrh addrl
+
Y Reg
effective address
The Western Design Center
W65C816S
21