W65C816S Datasheet, PDF (22/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
Absolute Indirect-(a)
With Absolute Indirect ((a)) addressing the second and third bytes of the instruction form an address to a pointer in
Bank 0. The Program Counter is loaded with the first and second bytes at this pointer. With the Jump Long
(JML) instruction, the Program Bank Register is loaded with the third byte of the pointer.
Instruction:
Indirect
OpCode
addrl
00
addrh
addrh
addrl
Absolute Long Indexed With X-al,x
With Absolute Long Indexed with X (al,x) addressing the second, third and fourth bytes of the instruction form a
24-bit base address. The effective address is the sum of this 24-bit address and the X Index Register.
Instruction:
Operand Address:
OpCode addrl
addrh
baddr
addrh
addrl
+
X Reg
effective address
baddr
Absolute Long-al
With Absolute Long (al) addressing the second, third and fourth byte of the instruction form the 24-bit effective
address.
Instruction:
Operand Address:
OpCode
baddr
addrl
addrh
addrh
addrl
baddr
Accumulator - A
With Accumulator (A) addressing the operand is the Accumulator.
Block Move-xyc
Block Move (xyc) addressing is used by the Block Move instructions. The second byte of the instruction contains
the high-order 8 bits of the destination address and the Y Index Register contains the low-order 16 bits of the
destination address. The third byte of the instruction contains the high-order 8 bits of the source address and the X
Index Register contains the low-order bits of the source address. The C Accumulator contains one less than the
number of bytes to move. The second byte of the block move instructions is also loaded into the Data Bank
Register.
Instruction:
OpCode dstbnk srcbnk
dstbnk Y DBR
Source Address:
srcbnk
X Reg
Dest. Address;
DBR
Y Reg
Increment X and Y (MVN) or decrement X and Y (MVP) and decrement C (if greater than zero), then PC=PC+3.
The Western Design Center
W65C816S
22