W65C816S Datasheet, PDF (25/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
Direct Indirect-(d)
With Direct Indirect ((d)) addressing the second byte of the instruction is added to the Direct Register to form a
pointer to the low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8 bits of
the effective address.
Instruction:
then:
+
Operand Address:
OpCode offset
Direct Register
+
offset
00
(direct address)
DBR
effective address
Direct-d
With Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to form the
effective address. An additional cycle is required when the Direct Register is not page aligned (DL not equal 0).
The Bank register is always 0.
Instruction:
Operand Address:
OpCode
+
00
offset
Direct Register
offset
effective address
Immediate-#
With Immediate (#) addressing the operand is the second byte (second and third bytes when in the
16-bit mode) of the instruction.
Implied-i
Implied (i) addressing uses a single byte instruction. The operand is implicitly defined by the instruction.
Program Counter Relative Long-rl
The Program Counter Relative Long (rl) addressing mode is used with only with the unconditional Branch Long
instruction (BRL) and the Push Effective Relative instruction (PER). The second and third bytes of the
instruction are added to the Program Counter, which has been updated to point to the OpCode of the next
instruction. With the branch instruction, the Program Counter is loaded with the result. With the Push Effective
Relative instruction, the result is stored on the stack. The offset is a signed 16-bit quantity in the range from
-32768 to 32767. The Program Bank Register is not affected.
The Western Design Center
W65C816S
25