W65C816S Datasheet, PDF (17/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
The Data/Bank Address Bus (D0-D7) pins provide both the Bank Address and Data. The bank address is present
during the first half of a memory cycle, and the data value is read or written during the second half of the memory
cycle. Two memory cycles are required to transfer 16-bit values. These lines may be set to the high impedance
state by the Bus Enable (BE) signal.
3.5 Emulation Status (E)
The Emulation Status (E) output reflects the state of the Emulation (E) mode flag in the Processor Status (P)
Register. This signal may be thought of as an OpCode extension and used for memory and system management.
3.6 Interrupt Request (IRQB)
The Interrupt Request (IRQB) negative level active input signal is used to request that an interrupt sequence be
initiated. When the IRQB Disable (I) flag is cleared, a low input logic level initiates an interrupt sequence after
the current instruction is completed. The Wait-for-Interrupt (WAI) instruction may be executed to ensure the
interrupt will be recognized immediately. The Interrupt Request vector address is 00FFFE,F (Emulation mode) or
00FFEE,F (Native mode). Since IRQB is a level-sensitive input, an interrupt will occur if the interrupt source was
not cleared since the last interrupt. Also, no interrupt will occur if the interrupt source is cleared prior to interrupt
recognition. The IRQB signal going low causes 4 bytes of information to be pushed onto the stack before jumping
to the interrupt handler. The first byte is PBR followed by PCH, PCL and P (Processor Status Register). These
register values are used by the RTI instruction to return the processor to its original state prior to handling the IRQ
interrupt (see Table 6-1)
3.7 Memory Lock (MLB)
The Memory Lock (MLB) active low output may be used to ens ure the integrity of Read-Modify-Write
instructions in a multiprocessor system. Memory Lock indicates the need to defer arbitration of the next bus cycle.
Memory Lock is low during the last three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB
memory referencing instructions, depending on the state of the M flag.
3.8 Memory/Index Select Status (MX)
The Memory/Index Select Status (MX) multiplexed output reflects the state of the Accumulator (M) and Index (X)
elect flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid during PHI2 negative transition and
Flag X is valid during PHI2 positive transition. These bits may be thought of as OpCode extensions and may be
used for memory and system management.
The Western Design Center
W65C816S
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