W65C816S Datasheet, PDF (18/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
3.9 Non-Maskable Interrupt (NMIB)
A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence. A high-to-low
transition initiates an interrupt sequence after the current instruction is completed. The Wait for Interrupt (WAI)
instruction may be executed to ensure that the interrupt will be recognized immediately. The Non-Maskable
Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B (Native mode). Since NMIB is an
edge-sensitive input, an interrupt will occur if there is a negative transition while servicing a previous interrupt.
No interrupt will occur if NMIB remains low after the negative transition was processed. The NMIB signal going
low causes 4 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first
byte on the stack is the PBR followed by the PCH, PCL and P, these register values are used by the RTI
instruction to return the processor to its original state prior to the NMI interrupt.
3.10 Phase 2 In (PHI2)
Phase 2 In (PHI2) is the system clock input to the microprocessor. PHI2 can be held in either state to preserve the
contents of internal registers and reduce power as a Standby mode.
3.11 Read/Write (RWB)
The Read/Write (RWB) output signal is used to control whether the microprocessor is "Reading" or "Writing" to
memory. When the RWB is in the high state, the microprocessor is reading data from memory or I/O. When
RBW is low the Data Bus contains valid data from the microprocessor which is to written to the addressed
memory location. The RWB signal is set to the high impedance state when Bus Enable (BE) is low.
3.12 Ready (RDY)
The Ready (RDY) is a bi-directional signal. When it is an output it indicates that a Wait for Interrupt (WAI)
instruction has been executed halting operation of the microprocessor. A low input logic level will halt the
microprocessor in its current state. Returning RDY to the active high state releases the microprocessor to continue
processing following the next PHI2 negative transition. The RDY signal is internally pulled low following the
execution of a Wait for Interrupt (WAI) instruction, and then returned to the high state when a RESB, ABORTB,
NMIB, or IRQB external interrupt is active. This feature may be used to reduce interrupt latency by executing the
WAI instruction and waiting for an interrupt to begin processing. If the IRQB Disable flag has been set, the next
instruction will be executed when the IRQB occurs. The processor will not stop after a WAI instruction if RDY
has been forced to a high state. The Stop (STP) instruction has no effect on RDY. The RDY pin has an active
pull-up and when outputting a low level, the pull-up is turned off to reduce power. The RDY pin can be wired
ORed.
The Western Design Center
W65C816S
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