W65C816S Datasheet, PDF (58/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
8.6 DB/BA operation when RDY is Pulled Low
When RDY is low, the Data Bus is held in the data transfer state (i.e. PHI2 high). The Bank address external
transparent latch should be latched on the rising edge of the PHI2 clock.
8.7 MX Output
The MX output reflects the value of the M and X bits of the processor Status Register. The REP, SEP and PLP
instructions may change the state of the M and X bits. Note that the MX output is invalid during the instruction
cycle following REP, SEP and PLP instruction execution. This cycle is used as the OpCode fetch cycle of the
next instruction.
8.8 All OpCode s Function in All Modes of Operation
8.7.1 It should be noted that all OpCodes function in all modes of operation. However, some instructions
and addressing modes are intended for W65C816S 24-bit addressing, and are therefore less useful for the
emulation mode. The JSL, RTL, JMP al and JML instructions and addressing modes are primarily intended for
W65C816S native mode use.
8.7.2 The following instructions may be used with the emulation mode even though a Bank Address is not
multiplexed on the Data Bus: PHK, PHB and PLB
8.7.3 The following instructions have "limited" use in the Emulation mode:
8.7.3.1 The REP and SEP instructions cannot modify the M and X bits when in the Emulation mode.
In this mode the M and X bits will always be high (logic 1).
8.7.3.2 When in the Emulation mode, the MVP and MVN instructions use the X and Y Index
Registers for the memory address. Also, the MVP and MVN instructions can only move data within the
memory range 0000 (Source Bank) to 00FF (Destination Bank) for the W65C816S, and 0000 to 00FF for the
emulation mode.
8.9 Indirect Jumps
The JMP (a) and JML (a) instructions use the direct Bank for indirect addressing, while JMP (a,x) and JSR
(a,x) use the Program Bank for indirect address tables.
8.10 Switching Modes
When switching from the Native mode to the Emulation mode, the X and M bits of the Status
Register are set high (logic 1), the high byte of the Stack is set to 01, and the high bytes of the X
and Y Index Registers are set to 00. To save previous values, these bytes must always be stored
before changing modes. Note that the low byte of the S, X and Y Registers and the low and high
byte of the Accumulator (A and B) are not affected by a mode change.
8.11 How Interrupts Affect the Program Bank and the Data Bank Registers
8.11.1 When in the Native mode, the Program Bank register (PBR) is cleared to 00 when a hardware
interrupt, BRK or COP is executed. In the Native mode, previous PBR contents are automatically saved on
Stack.
8.11.2 In the Emulation mode, the PBR and DBR registers are cleared to 00 when a hardware
interrupt, BRK or COP is executed. In this case, previous contents of the PBR are not automatically saved.
8.11.3 Note that a Return from Interrupt (RTI) should always be executed from the same
"mode" which originally generated the interrupt.
The Western Design Center
W65C816S
58